An indirect VLIW processor is organized with a VLIW memory (VIM) that is separate from its short instruction word (SIW) memory. The VIM is defined for an instruction set architecture by way of specific SIWs that control the loading and execution of the VLIWs stored in the VIM. For example, a load VLIW (LV) instruction is defined which acts as a setup control delimiter instruction for the processor logic. The LV instruction specifies the VIM address where a VLIW is to be stored and the number of SIWs which follow the LV instruction that are to be stored at the specified VIM address in VLIW fashion. Another special SIW is the execute VLIW (XV) instruction. The XV instruction causes a VLIW to be read out of VIM at the XV specified address.
The ManArray processor defines two preferred architectures for indirect VLIW memories. One approach treats the VIM as one composite block of memory using one common address interface to access any VLIW stored in the VIM. The second approach treats the VIM as made up of multiple smaller memories each individually associated with the functional units and each individually addressable for loading and reading during XV execution. It will be recognized that improved techniques loading of VLIW memory will be highly desirable.